Website der Veranstaltung
Although the basic reliability of hardware and software components has
improved over decades, their increasing number causes severe problems.
Moreover, in recent years it can be observed that in an increasing
number of devices, e.g. cars, digital components are integrated into
environments of other physical components. Here, the complexity and
number of interactions with these components creates problems with
regard to maintaining a dependable operation of the entire system in
case of faults or external disturbances.
While this is not a problem with microprocessors there, shrinking
feature sizes, higher complexity, lower voltages, and higher clock
frequencies increase the probability of design-, manufacturing-, and
operational faults, making fault tolerance techniques in general purpose
processors to be of crucial importance in the future. As simple
solutions (such as TMR) easily can get too expensive, the ability to
trade increased reliability against performance/power overhead will
become important, resulting in light-weight fault tolerance techniques
implemented in hardware, but controllable from higher software layers.
This workshop aims at presenting contributions and work-in-progress from
the research area of dependable and fault tolerant computing in order to
bring together scientists working in related fields.